This invention relates to design automation methods for designing digital electronic circuits. The invention is particularly concerned with electronic circuits, such as very large scale integrated (VLSI) circuits, having built-in self-test (BIST) facilities.
Referring to FIG. 1, this shows a typical digital electronic circuit with BIST facilities. The circuit consists of a number of blocks of logic (logic A-C) interconnected by a number of self-test registers (register 1-5). Each of these self-test registers is designed to have at least the following modes of operation:
(a) User--in this mode the self-test register acts as a conventional parallel input/output latch. PA1 (b) Random--in this mode, the self-test register operates as a linear feedback shift register (LFSR) for generating a pseudo-random sequence of test patterns. PA1 (c) Signature--in this mode, the self-test register operates as an LFSR for receiving a sequence of input data, and generating a digital signature, characteristic of the input data sequence. PA1 (d) Shift--in this mode the self-test register acts as a serial shift register, allowing test patterns to be shifted into the register, and allowing signatures to be shifted out. PA1 (a) identifying a set of driving bits for each of a set of points within the tree; PA1 (b) for each of said set of points, identifying a set of splittable input bits that can be isolated by insertion of a fence register at that point; PA1 (c) identifying which of said points are possible fence points, having more than one splittable input bit; and PA1 (d) selecting a sub-set of said possible fence points, sufficient to reduce the number of inputs to the logic tree to a value less than a predetermined limit, and inserting fence registers at those points.
The use of such test registers for BIST is described, for example in European Patent No. 0196171 (U.S. Pat. No. 4,701,916). [C1005]
In normal operation, each of these self-test registers is set into its user mode, so that they all act as conventional latches. In order to test logic block A, for example, register 1 is set into the random mode so as to generate a pseudo-random sequence of test patterns at the inputs of logic block A. At the same time, register 3 is set into the signature mode, so as to collect a series of outputs from logic block A, and to form a digital signature. When the test sequence is completed, the registers are all switched to the shift mode, to allow the test results to be serially shifted out over a serial path, and the generated signature is then compared with an expected signature value. If these values are not equal, a fault is indicated.
Referring to FIG. 2, this shows a typical logic block. The logic block consists of a number of logic cells (such as AND gates, NAND gates, OR gates, and so on), represented schematically as rectangles in the drawing, connected together in a network, between a number of inputs (I1-I26) and a number of outputs (O1-O3).
It can be seen from this Figure that it is possible to trace a tree back from each of the outputs, to find the set of inputs that influence that output. In this example, output O1 is influenced by inputs I1-I20, output O2 is influenced by inputs I15-I22, and output O3 is influenced by inputs I23-I26.
In order to test a logic block thoroughly, it is desirable to apply an exhaustive sequence of data patterns to the inputs of each such tree, so as to test the response of the logic to all possible input patterns. However, a problem with this is that if a tree is too large (i.e. has too many inputs), exhaustive testing will take an excessively long time. It has been found in practice that the maximum feasible number of inputs to any given tree for exhaustive testing is about 17. In FIG. 2, for example, the tree traced back from output O1 has 20 inputs, and so, on this criterion, it would not be economically feasible to exhaustively test this tree. On the other hand, the tree traced from output O2 has only 8 inputs, and so exhaustive testing would be feasible.
One way of overcoming this problem is to partition the logic block, by inserting additional self-test registers, referred to herein as fences, in such a manner that each fence bit splits off two or more input bits of a tree, i.e. isolates those input bits from the output of the tree. By inserting a sufficient number of fences in suitable locations, the tree can be reduced to an acceptable size. For example, in FIG. 2, the logic block could be partitioned by inserting a fence at the position indicated by *, so as to divide the tree into two independently testable sub-trees. It can be seen that the fence replaces the five inputs I1-I5 in the large tree with a single input, and so reduces the number of inputs that influence output O1 to 16.
However, the problem still remains of where to position the fences, and how many fences are required, and this can be very difficult and time consuming. The problem is particularly acute where the logic has been generated automatically, by a logic synthesis program, since in that case it is quite likely that the synthesized logic will contain many large trees, and the logic designer will not be familiar with the generated logic.
The object of the present invention is to provide a way of alleviating this problem.